Such frequency-divider circuitry may be configured to switch between two different values of Di, such as Di1 and Di2. Alternatively, two sets of frequency-divider circuitry could be provided having such different values of Di, and their outputs could be switched between. By switching between Di1 and Di2, a fractional frequency divider may be provided where the target output clock signal CLKout stabilises at a frequency which is between Di1 and Di2 (i.e. at the time average of Di1 and Di2). The present disclosure will be understood accordingly.
Such frequency-divider circuitry may be referred to as a clock divider. Such circuitry finds wide use, to provide a target clock signal based on a reference clock signal (e.g. from an oscillator or other clock source) for any circuitry operable based on such a target clock signal. For example, most integrated circuits (ICs) use one or more clock signals to synchronise or otherwise control different parts of system circuitry. Circuits operating based on clock signals may thus be considered synchronous circuits. Examples include processing circuits such as audio-processing circuits.
Frequency-divider circuitry therefore may be implemented on ICs or systems within a host device, which may be considered an electrical or electronic device. Examples include a portable and/or battery powered host device such as a mobile telephone, an audio player, a video player, a PDA, a mobile computing platform such as a laptop computer or tablet and/or a games device.
Existing frequency-divider circuitry has been found to have shortcomings, in particular when more than one divider ratio Di may be needed (in a single IC or application, or across different ICs or applications). It is accordingly desirable to provide improved frequency-divider circuitry, for example where the reference clock signal CLKin and/or divider ratio Di can readily be configured.